Earlier this year, 1366 Technologies elevated Dr. Adam Lorenz to the position of Chief Technology Officer. A founding member of the Company, Adam has played a pivotal role in moving the Direct Wafer® technology from prototype to commercial readiness. Here, he comments on 1366’s recent efficiency achievements as well as the Company’s technical road map.

What challenges does the PV industry face?
Solar is now the cheapest form of generating electricity in many parts of the world, and this will continue to spread.  The biggest challenge facing manufacturers is extreme pressure to reduce cost, which is becoming increasing difficult with today’s manufacturing processes.  The current supply chain has been streamlined around processes that are 30+ years old.

How do you see 1366 helping to solve these challenges?
The current ingot casting and sawing processes are the most wasteful steps in silicon PV manufacturing, both from a material and energy standpoint.  It is truly a shame to take the most highly-purified material on the planet (9N purity silicon after refining by Siemens) and throw half of it away as useless sludge.  The Direct Wafer process is an elegant alternative to fabricate premium silicon PV wafers without wasting silicon and using far less energy.  Since wafers represent 40% of the cost of today’s PV modules, our impact is very significant.

1366 has witnessed rapid efficiency gains these last few months. What do you attribute those gains to?
Over the past several years, our continuous advancement in wafer quality has alternatively focused on improving purity, dislocations and grain structure.   Most recently, our team has implemented improvements to the nucleation behavior and resulting crystal structure and we have combined this with the first stages of implementing a dopant gradient. This has enabled us, for the first time late last year, to beat the cell efficiency of our reference multicrystalline material on a head-to-head basis.

Can you talk more about the Direct Wafer technology’s efficiency potential?
The efficiency potential of our wafers will of course be determined by the cell architectures used, and what we’ve been able to demonstrate using PERC is that our performance today is on par with high performance multicrystalline (HPM) wafers. In fact, our advantages of better microstructure and improved consistency will allow us to far surpass HPM, delivering a superior product with significant cost and technical advantage. An exciting benefit of our wafers is that all of the improvements of industry cell efficiency road maps will be transferable to our material. This extends beyond single junction materials and enables us to use Direct Wafer products for tandem cells that could exceed 30% efficiency.

Working at the melt level rather than an ingot unleashes the potential for a lot more wafer innovation. What are some of the more exciting things you’re doing here?
In the near term, and this is something I mentioned earlier, we have a unique ability to create a grown-in doping gradient with higher dopant concentration on the rear side of each wafer. This is a powerful tool that enables more efficient carrier collection, higher voltages and a higher fill factor because of better conductivity through the bulk of the wafer. This bonus feature is simply not possible with any wafer sawn from a block.

The Direct Wafer process grows wafers with a more uniform microstructure. Can you explain how that’s achieved and why it’s important?
A recent innovation in directionally-solidified ingot material is to seed the crucible floor to achieve a fine-grain, equiaxed microstructure at the bottom portion of the ingot. Wafers sliced from this region typically have fewer structural defects because dislocations have not yet had the opportunity to propagate.  A challenge for HPM is to attempt to maintain that microstructure by controlling the heat transfer and minimizing thermal stress while solidifying and cooling the rest of the ingot over 24+ hours.  During that time, impurities diffuse from the walls and contaminate what was previously the best wafers (based on microstructure). In the Direct Wafer process, we have extremely good control over the growth environment for each individual wafer and the fresh nucleation that occurs each time does not allow propagation of dislocations.  We achieve small equiaxed grains, similar to the bottom of an HPM ingot, and eliminate the variation that occurs from bottom to top and center to edge in traditional casting.  Solidification and cooling of each wafer is completed in a matter of seconds, not days – enabling higher purity along with the low dislocation density.

You spoke last year at EUPVSEC on 1366’s ability to grow a thin wafer with a thick border. Why is that significant?
For many years, the PV industry has wanted to move to thinner wafers to reduce cost but the execution has been challenging because of wafer breakage during cell handling and interconnection during module making. Silicon is a brittle material and behaves like glass, with breakage typically starting at the outside edges. Because 1366’s Direct Wafer process allows for local control of wafer thickness, we can produce a thin wafer that has thicker reinforcement where needed at the edges. Designing a 3D wafer can reduce the total volume of silicon required for each wafer and significantly reduce cost without sacrificing strength, durability or performance.

You’ve been with the Company since its inception. Looking back over the years, what technical achievements are you most proud of?

It has been a privilege to work with such a talented team of engineers, working hard to come up with solutions that will have a great impact making worldwide electricity production cleaner. The remarkable progress we have made improving cell efficiency ~1%/year has been a culmination of hundreds of different small improvements and innovations that have been contributed from all facets of our team – machine design, control systems, material characterization and process engineering. In 2013, I was excited when we made our first 16% cell on a 156mm wafer and demonstrated in a very real way that we could produce meaningful product using our new manufacturing process. Four years later and with the collaborative efforts of our partners, approaching 20% efficiency is also exciting. These efficiency milestones are the result of hundreds of different things happening correctly and they are a testament to the impressive work we’ve done together as a team. I certainly enjoy the opportunities to see our product being processed through high volume production lines, further demonstrating that we are now ready to scale.